DocumentCode
2547105
Title
Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis
Author
Goldberg, S. ; Upadhyaya, S.J.
Author_Institution
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
fYear
1995
fDate
13-15 Nov 1995
Firstpage
234
Lastpage
242
Abstract
Defining a dual role for spare processing elements (PEs) in reliability-challenged processing arrays is the major focus of the paper. The paper also explores a practical way to include reconfiguration hardware in single-package arrays. The implementation of array processor systems may include spare PE´s for fault tolerance. These systems typically require a host for fault diagnosis, while the healthy spares sit idle. It is proposed to utilize the idling spare PEs for purposes of fault diagnosis, giving the array the capability of self diagnosis. Fault tolerance must incorporate additional hardware for reconfiguration, and existing plans have not found widespread use in single-package systems due to the extra cost and extra real estate. Multichip modules (MCMs) have the potential to offer fault tolerance with no increase in primary circuit area. It is proposed to contain the reconfiguration hardware in the active substrate of a silicon-based MCM. Further, the switches required for spares coverage can aid in the job of comparison based self-testing. We offer a complete solution to fault-tolerant arrays in the sense that diagnosis, reconfiguration and switching details are all addressed
Keywords
fault diagnosis; fault tolerant computing; multichip modules; parallel processing; reliability; wafer-scale integration; array processor systems; fault coverage; fault diagnosis; fault tolerance; multichip modules; primary circuit area; reconfiguration hardware; reliability-challenged processing arrays; self diagnosis; spare processing elements; spares coverage; switching details; Circuit faults; Costs; Fault diagnosis; Fault tolerance; Fault tolerant systems; Hardware; Multichip modules; Switches; System testing; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location
Lafayette, LA
ISSN
1550-5774
Print_ISBN
0-8186-7107-6
Type
conf
DOI
10.1109/DFTVS.1995.476957
Filename
476957
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