Fast timing analysis of plane circuits via two-layer CNN-based modeling

A fast timing analysis of plane circuits via two-layer CNN-based modeling, which is necessary for the solution of power/signal integrity problems in printed circuit boards and packages, is presented. Using the new notation expressed by the two-layer CNN, more than 1500 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration algorithms such as the forward Euler and Runge-Kutta methods. However, since the system of the two-layer CNN becomes stiff, we cannot analyze the CNN by using an explicit numerical integration algorithm. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced in this paper. This procedure would open a CNN application up to electronic design automation area