Investigation of inductors for digital Si-CMOS technologies

This paper investigates the performance of passive and active inductors for digital Si-CMOS technologies. The extreme low-resistivity of the Si-substrate and the absence of thick top metal layers in digital-CMOS processes prevent the implementation of high-Q passive inductors, and demand alternate solutions. A detailed comparison between the active and passive inductors based on several performance criteria such as Q-factor, area, tunability, noise, linearity, EMI, floor-planning etc reveals the tremendous potential of the high-Q tunable active inductors. An optimization guideline for the grounded-inductor topology has also been suggested. As a basis of comparison, oscillators have been implemented using both the inductors. The active inductor VCO achieves a much higher tuning range and occupies a much smaller die-area than the passive implementation at the cost of degraded phase-noise performance