Title :
FFT-based test of a yield monitor circuit
Author :
Thibeault, C. ; Payeur, A.
Author_Institution :
Dept. of Electr. Eng., Ecole de Technol. Superieure, Montreal, Que., Canada
Abstract :
In this paper, we present a simple way to improve an existing electrical defect identification and location method. We show that replacing the DC voltage analysis by an FFT voltage analysis allows to reduce by a factor of about two the number of test vectors required to locate and identify defects on a yield monitor chip. Moreover, we suggest a minor modification to the monitor, doubling the reduction factor. Simulations results show that the location and identification potential is preserved
Keywords :
VLSI; fast Fourier transforms; integrated circuit testing; integrated circuit yield; production testing; FFT-based test; electrical defect identification; identification potential; reduction factor; test vectors; yield monitor circuit; Circuit simulation; Circuit testing; Integrated circuit yield; Manufacturing processes; Monitoring; Optical buffering; Production; Statistics; Very large scale integration; Voltage;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1995. Proceedings., 1995 IEEE International Workshop on,
Conference_Location :
Lafayette, LA
Print_ISBN :
0-8186-7107-6
DOI :
10.1109/DFTVS.1995.476958
