A low-power 2-GSample/s comparator in 120 nm CMOS technology

Author

Goll, Bernhard ; Zimmermann, Horst

Author_Institution

Inst. fur elektrische Mess- und Schaltungstechnik, Technische Univ. Wien, Austria

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

507

Lastpage

510

Abstract

This paper presents a comparator in 120nm digital CMOS technology with a supply voltage of 1.5V. In contrast to common comparator structures a delayed reset signal is used to enhance the output voltage difference with the help of charge injection. Furthermore the body effect of p-MOS transistors with their separated n-wells are used to lower their threshold voltage to have an increase in resolution. For characterization several BER (bit-error-rate) measurements on the comparator have been made. For a BER of 109 the comparator is able to detect an input voltage difference of 9.5mV at a clock frequency of 1.5GHz and 16mV at 2.0GHz. The maximum power consumption of the comparator with two following additional transfer stages is 360μW at 2.0GHz.

Keywords

CMOS digital integrated circuits; comparators (circuits); error statistics; integrated circuit design; low-power electronics; 1.5 V; 1.56 GHz; 120 nm; 16 mV; 2 GHz; 360 muW; 9.5 mV; bit error rate measurements; charge injection; delayed reset signal; digital CMOS technology; low-power comparator; p-MOS transistors; Bit error rate; CMOS technology; Circuits; Delay; Force feedback; Inverters; Latches; Switches; Threshold voltage; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European

Print_ISBN

0-7803-9205-1

Type

conf

DOI

10.1109/ESSCIR.2005.1541671

Filename

1541671