Fine grained multi-threshold CMOS for enhanced leakage reduction

The exponential increase in leakage power due to technology scaling has made multi-threshold CMOS (MTCMOS) an attractive design style for low-power applications. We explore this design style in a datapath and introduce a fine grained power gating approach to better exploit the power-performance tradeoff. We propose a power gating technique where the degree of power gating applied becomes progressively stronger further along the datapath