Title :
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers
Author :
Kurose, Daisuke ; Ito, Tomohiko ; Ueno, Takeshi ; Yamaji, Takafumi ; Itakura, Tetsuro
Author_Institution :
Corporate R&D Center, Toshiba Corp., Kawasaki, Japan
Abstract :
A new power reduction technique for ADCs is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique, and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-P 7-M CMOS technology. The 10-bit, 200-MSPS ADCs achieve DNL of 0.66 LSB, rNL of 1.00 LSB, and SNDR of 54.4 dB that corresponds to 8.7 ENOB. The power dissipation is only 55 mW from a 1.2-V supply.
Keywords :
CMOS integrated circuits; amplifiers; analogue-digital conversion; integrated circuit design; low-power electronics; radio receivers; 1.2 V; 55 mW; 90 nm; CMOS technology; amplifier sharing technique; pipeline ADC; power reduction technique; wireless receivers; CMOS technology; Circuits; Digital filters; Energy consumption; Mobile communication; Operational amplifiers; Pipelines; Power amplifiers; Power dissipation; Sampling methods;
Conference_Titel :
Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European
Print_ISBN :
0-7803-9205-1
DOI :
10.1109/ESSCIR.2005.1541676
