High fan-in differential current mirror logic

A new differential current mirror logic (DCML) family is presented. It is based on a dynamic differential topology and uses current mirrors to enhance current sensing and a sense amplifier to speed up output evaluation. Its performance in terms of delay, power and area is compared to that of cross coupled differential domino (CCDD) logic. Simulations, using a 0.18mum technology to implement high fan-in XOR/XNOR gates, were utilized to evaluate the performance of the two topologies. It is shown that for fan-ins higher than 4 the proposed logic family presents increasing reduction in delay and energy against single and multi-stage CCDD implementations, with the single-stage CCDD circuits degrading fast and being inefficient for fan-ins higher than 10. In parallel, the silicon area penalty of the DCML towards single-stage CCDD is very small and constant regardless of the gate fan-in, while multi-stage CCDDs take a much grater area than DCML which increases with the number of gates used in the multi-stage implementation