S-LINK on a Chip for Embedded Applications

S-LINK [1] is a custom data transmission protocol developed at CERN, which has been used in some of the data acquisition systems of the LHC experiments. S-LINK was released in the late ´90s and is based on a simple FIFO-like user interface, which remains independent of the technology used to implement the physical layer. According to the increasing request for higher density, bandwidth and embedded applications, we developed a singlechip version of the S-LINK board (HOLA) widely deployed in the ATLAS experiment. Our architecture is based on latest generation Xilinx FPGA with high-speed serial transceivers in the multi Gb/s domain. Specific implementation flavours target different requirements: increasing the bandwidth performances of the link, keeping it backward compatible with the HOLA card based on a commercial SerDes (TLK2501), adding fixed-latency for real-rime critical operations. In this paper we describe the S-LINK implementation details and some of the measurements carried out. Specifically, we present and discuss the performance in terms of bandwidth, BER, backward compatibility and fixed latency. Resource occupation is also addressed in the view of a possible IP release.