Title :
SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis
Author :
Manimegalai, R. ; Jayaram, B. ; Manojkumar, A. ; Kamakoti, V.
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Madras, Chennai, India
Abstract :
This work discusses the technology mapping problem on hybrid field programmable architectures (HFPA). HFPAs are realized using a combination of lookup tables (LUTs) and programmable logic arrays (PLAs). HFPAs provide the designers with the advantages of both LUT-based field programmable gate arrays (FPGA) and PLAs. Specifically, the use of PLAs leads to reduced area in mapping the given circuit. Designing of technology mapping methodologies which map a given circuit on to the HFPA that exploits the above-mentioned advantages is a problem of great research and commercial interest. This work presents SHAPER, which maps the circuits onto HFPAs using reconvergence analysis. Empirically, it is shown that SHAPER yields better area-reduction than the previous known algorithms.
Keywords :
field programmable gate arrays; integrated circuit layout; logic design; table lookup; LUT-based field programmable gate arrays; SHAPER; circuit mapping; complex programmable logic devices; hybrid FPGA; hybrid field programmable architectures; lookup tables; programmable logic arrays; reconvergence analysis; technology mapping; Circuit synthesis; Field programmable gate arrays; Logic arrays; Logic devices; Logic functions; Programmable logic arrays; Programmable logic devices; Random access memory; Read-write memory; Table lookup;
Conference_Titel :
Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
Print_ISBN :
0-7803-8651-5
DOI :
10.1109/FPT.2004.1393251
