Title :
A new current-mode incremental signaling scheme with applications to Gb/s parallel links
Author :
Wang, Tao ; Yuan, Fei
Author_Institution :
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont.
Abstract :
A new current-mode incremental signaling scheme for high-speed parallel links is proposed. The signaling scheme requires only N+1 physical paths for N parallel bits. It possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low switching noise injection, and superior signal integrity. The current-integrating front-end offers the key advantages of a low and tunable input impedance for channel termination, large bandwidth, and effective suppression of high-frequency noise coupled to the channels. Simulation results of a 4-bit parallel link implemented in a 0.13 mum, 1.2V CMOS technology demonstrate that the proposed signaling scheme is capable of transmitting parallel data at 10 Gbps
Keywords :
CMOS integrated circuits; current-mode circuits; integrated circuit design; 0.13 micron; 1.2 V; 10 Gbit/s; 4 bit; CMOS technology; channel termination; circuit simulation; current-mode incremental signaling; high-speed parallel links; low switching noise injection; parallel bits; physical paths; signal integrity; Application software; CMOS technology; Driver circuits; Fluctuations; Impedance; Resistors; Signal mapping; Transmitters; Tunable circuits and devices; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693512
