Stream applications on the dynamically reconfigurable processor

Author

Suzuki, Masayasu ; Hasegawa, Yohei ; Yamada, Yutaka ; Kaneko, Naoto ; Deguchi, Katsuaki ; Amano, Hideharu ; Anjo, Kenichiro ; Motomura, Masato ; Wakabayashi, Kazutoshi ; Toi, Takao ; Awashima, Tom

Author_Institution

Graduate Sch. of Sci. & Technol., Keio Univ., Yokohama, Japan

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

137

Lastpage

144

Abstract

Dynamically reconfigurable processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C67J3 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

Keywords

integrated circuit design; logic circuits; microprocessor chips; pipeline processing; reconfigurable architectures; DRP-1; DSP TMS320C67J3; NEC Electronics; Pentium III/4; Texas Instruments; circuit configurations; data path selection; dynamically reconfigurable processor; embedded CPU MIPS64; execution pipelining; on-chip repository; programming techniques; stream application; stream applications; Boosting; Digital signal processing chips; Dynamic programming; Instruments; Logic circuits; Logic programming; National electric code; Pipeline processing; Prototypes; Reconfigurable logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Print_ISBN

0-7803-8651-5

Type

conf

DOI

10.1109/FPT.2004.1393261

Filename

1393261