A low power merge cell processor for real-time spike sorting in implantable neural prostheses

Extremely low power consumption is the critical constraint for designing implantable neural decoders that interface directly with the nervous system. Typically a system with such strict constraints is implemented as an ASIC; however, the rapid progress in the field mandates a more flexible solution. In this paper we introduce a new general architecture, the Merge Framework, and its low power implementation for real-time spike sorting in cortical control applications, that offers a flexible and powerful programming model with near ASIC power efficiency