The new improved pseudo fractional-N clock generator with 50% duty cycle

Author

Kuo, Shu-Chang ; Hung, Tzu-Chien ; Yang, Wei-Bin

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu

fYear

2006

fDate

21-24 May 2006

Abstract

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to generate the needed frequencies with 50% duty cycle. Further, we propose a design flowchart to solve the problem of pseudo fractional-N clock generator. The circuits are processed in a standard 0.13mum CMOS technology, and work with a supply voltage of 1.2V

Keywords

CMOS integrated circuits; clocks; phase locked loops; system-on-chip; voltage-controlled oscillators; 0.13 micron; 1.2 V; CMOS technology; phase-locked loop; pseudo fractional-N clock generator; system-on-chip; voltage-controlled oscillator; CMOS process; CMOS technology; Circuits; Clocks; Flowcharts; Frequency; Phase locked loops; System-on-a-chip; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693547

Filename

1693547

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2549423