FPGA implementation of hierarchical memory architecture for network processors

One of the key design issues for network processors (NPs) is hiding long latency of random off-chip memory accesses. We present a novel memory subsystem especially for access and edge routers to implement feature-rich network applications with wire-speed processing guarantees. Because of the hierarchical organizations specially designed for network circumstances, access latency of DRAM is totally hidden and the number of off-chip memory accesses can also be reduced. We implement this architecture based on a simplified OpenRISC processor core in an Altera Stratix EP1S20B672 FPGA. Time analysis shows that this memory subsystem achieves an operating frequency of over 200MHz, with approximately 2% LEs and 1% memory resources.