Title :
High-performance, low-power skewed static logic in very deep-submicron (VDSM) technology
Author :
Kim, Chulwoo ; Lee, Jaesik ; Baek, Kwang-Hyun ; Martina, Eric ; Kang, Sung-Mo Steve
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
This paper presents S2L, which exhibits low-power, high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S2L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S2L compared to other techniques. Design automation for the proposed circuit architecture can be achieved easily due to cascading flexibility
Keywords :
adders; circuit simulation; electronic design automation; feedback; logic circuits; logic design; NAND-NOR gate chains; S2L; adders; dual Vt; leakage current; low-power skewed static logic; performance; positive feedback circuits; simulation results; topology-dependent dual Vt approach; very deep-submicron technology; CMOS logic circuits; CMOS technology; Circuit noise; Circuit synthesis; Clocks; Energy consumption; Flexible printed circuits; Leakage current; Logic circuits; MOS devices;
Conference_Titel :
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-0801-4
DOI :
10.1109/ICCD.2000.878269
