High-performance, low-power skewed static logic in very deep-submicron (VDSM) technology

Author

Kim, Chulwoo ; Lee, Jaesik ; Baek, Kwang-Hyun ; Martina, Eric ; Kang, Sung-Mo Steve

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

fYear

2000

fDate

2000

Firstpage

59

Lastpage

64

Abstract

This paper presents S²L, which exhibits low-power, high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S²L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S²L compared to other techniques. Design automation for the proposed circuit architecture can be achieved easily due to cascading flexibility

Keywords

adders; circuit simulation; electronic design automation; feedback; logic circuits; logic design; NAND-NOR gate chains; S²L; adders; dual Vt; leakage current; low-power skewed static logic; performance; positive feedback circuits; simulation results; topology-dependent dual Vt approach; very deep-submicron technology; CMOS logic circuits; CMOS technology; Circuit noise; Circuit synthesis; Clocks; Energy consumption; Flexible printed circuits; Leakage current; Logic circuits; MOS devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2000. Proceedings. 2000 International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-0801-4

Type

conf

DOI

10.1109/ICCD.2000.878269

Filename

878269