Title :
Probabilistic Analysis of Nanoscale XOR Gate
Author :
Lu, Xiao-Jun ; Li, Jian-ping
Author_Institution :
Sch. of Comput. Sci. & Eng, Univ. of Electron. Sci. & Technol. of China, Chengdu
Abstract :
The device failure must be taken into account in the nano-scale design. This paper presents the probabilistic logic model to model the probabilistic behavior of a nanoscale adder. The analysis shows that the device probability distribution highly depends on the system structures and other performance parameters.
Keywords :
logic gates; probability; device failure; nanoscale XOR gate; nanoscale adder; probabilistic analysis; probabilistic logic model; Circuits; Computer science; Design engineering; Failure analysis; Markov random fields; Nanoscale devices; Probabilistic logic; Probability density function; Probability distribution; Wavelet analysis; Nanoscale; XOR gate; probabilistic logic;
Conference_Titel :
Apperceiving Computing and Intelligence Analysis, 2008. ICACIA 2008. International Conference on
Conference_Location :
Chengdu
Print_ISBN :
978-1-4244-3427-5
Electronic_ISBN :
978-1-4244-3426-8
DOI :
10.1109/ICACIA.2008.4769958
