Worst delay estimation in crosstalk aware static timing analysis

Digital circuits manufactured in deep sub-micron technologies may experience crosstalk induced delay and noise signals. Crosstalk induced delay can be quite significant and difficult to determine because of dependency on switching time of the neighboring signals. We study the problem of computing signal earliest and latest arrival time when timing windows and slew rate ranges of the inputs and coupling neighbors´ inputs are known. We propose a complexity O(n log n) algorithm to solve this problem. The proposed method has been applied in crosstalk aware static timing analysis to guide timing driven layout synthesis. Experimental results have demonstrated its efficacy and efficiency.