A parameterizable HandelC divider generator for FPGAs with embedded hardware multipliers

Author

Hopf, John

Author_Institution

Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

355

Lastpage

358

Abstract

This work presents a parameterizable tool that generates HandelC code to perform fast division on FPGAs. With the introduction of VirtexII family FPGAs, fast division is now achievable by exploiting 18-bit hardware multipliers and fast block RAM (BRAM). Look up tables (LUTs) are used to store reciprocals of the denominators that are used in conjunction with the multiplier. This produces a low latency divider that consumes very little FPGA area, but at the cost of precision. In image processing applications, these properties are ideal.

Keywords

digital arithmetic; dividing circuits; embedded systems; field programmable gate arrays; multiplying circuits; random-access storage; table lookup; 18 bit; BRAM; HandelC code generation; VirtexII family FPGA; embedded hardware multipliers; fast block RAM; image processing applications; look up tables; parameterizable HandelC divider generator; parameterizable tool; Application software; Concurrent computing; Embedded computing; Field programmable gate arrays; Hardware; High level languages; Image fusion; Image processing; Lakes; Parallel processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Print_ISBN

0-7803-8651-5

Type

conf

DOI

10.1109/FPT.2004.1393298

Filename

1393298