Title :
Rigorous system level modeling and analysis of mixed HW/SW systems
Author :
Bourgos, P. ; Basu, A. ; Bozga, M. ; Bensalem, S. ; Sifakis, J. ; Huang, K.
Author_Institution :
VERIMAG, UJF-Grenoble 1, Grenoble, France
Abstract :
A grand challenge in complex embedded systems design is developing methods and tools for modeling and analyzing the behavior of an application software running on multicore or distributed platforms. We propose a rigorous method and a tool chain that allows to obtain a faithful model representing the behavior of a mixed hardware/software system from a model of its application software and a model of its underlying hardware architecture. The system model can be simulated and analyzed for validation of both functional and extra-functional properties. The tool chain uses DOL (Distributed Operation Layer [1]) as the frontend for specifying the application software and hardware architecture, and BIP (Behavior Interaction Priority [2]) as the modeling and analysis framework. It is illustrated through the construction of system models of MJPEG and MPEG2 decoder applications running on MPARM, a multicore architecture.
Keywords :
embedded systems; hardware-software codesign; multiprocessing systems; HW/SW systems; behavior interaction priority; distributed operation layer; embedded systems; hardware architecture; hardware/software system; software architecture; system level modeling; Analytical models; Application software; Computer architecture; Hardware; Indexes; Program processors;
Conference_Titel :
Formal Methods and Models for Codesign (MEMOCODE), 2011 9th IEEE/ACM International Conference on
Conference_Location :
Cambridge
Print_ISBN :
978-1-4577-0117-7
Electronic_ISBN :
978-1-4577-0118-4
DOI :
10.1109/MEMCOD.2011.5970506