Controller synthesis for pipelined circuits using uninterpreted functions

We present a novel abstraction-based approach to controller synthesis based on the use of a logic with uninter-preted functions, arrays, equality, and limited quantification. Extending the Burch-Dill paradigm for the verification of pipelined processors, we show how to use this logic to synthesize the Boolean control of a pipelined circuit, using a sequential version as the specification. Thus, we tackle the main difficulty in constructing concurrent systems, that of constructing a control that prevents conflicts due to concurrency. At the same time, we avoid the complexity of the datapath, taking advantage of the fact that it must mirror the operations in the sequential variant. We start with the controller´s specification, an equivalence criterion written in a fragment of second-order logic, stating that for all possible inputs/states, there exist Boolean control values such that the outcome is correct. We show how to decide such formulas by a reduction to propositional logic. From this formula, we can then extract the controller. We show preliminary results for a simple pipelined system.