• DocumentCode
    2550101
  • Title

    Power-sensitive multithreaded architecture

  • Author

    Seng, John S. ; Tullsen, Dean M. ; Cai, George Z N

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    199
  • Lastpage
    206
  • Abstract
    The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, but also change the way modern processors are architected. A multithreading processor is attractive in the context of low-power or power-constrained devices for many of the same reasons that enable its high throughput. Primarily, it supplies extra parallelism via multiple threads, allowing the processor to rely much less heavily on speculation. We show that a simultaneous multithreading processor utilizes up to 22% less energy per instruction than a single-threaded architecture. We also explore other power optimizations that are particular to multithreaded architectures, either because they are unavailable to or unreasonable for single-thread architectures
  • Keywords
    microprocessor chips; multi-threading; performance evaluation; power consumption; high-performance processors; low-level design; microprocessors; power-sensitive multithreaded architecture; simultaneous multithreading processor; Clocks; Computer architecture; Energy consumption; Microprocessors; Mobile computing; Multithreading; Parallel processing; Power dissipation; Throughput; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2000. Proceedings. 2000 International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-0801-4
  • Type

    conf

  • DOI
    10.1109/ICCD.2000.878286
  • Filename
    878286