DocumentCode
2550308
Title
Energy-efficient adaptive clocking dual edge sense-amplifier flip-flop
Author
Liu, Yen-Ting ; Chiou, Lih-Yih ; Chang, Soon-Jyh
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan
fYear
2006
fDate
21-24 May 2006
Lastpage
4332
Abstract
In this paper, we propose two novel dual edge-triggered flip-flops. One design eliminates redundant transitions of internal nodes when current data is the same as the previous one. This has the least power delay product compared to other dual edge-triggered flip-flops in all range of possible data switching activity and its delay is also the smallest. The other proposed flip-flop disables internal clocked transistors. When data switching activity is within 20%, it has the least power consumption
Keywords
circuit reliability; flip-flops; trigger circuits; data switching activity; dual edge-triggered flip-flops; energy-efficient adaptive clocking; internal clocked transistors; power delay product; sense-amplifier flip-flop; Capacitance; Circuits; Clocks; Delay; Energy consumption; Energy efficiency; Flip-flops; Frequency; Inverters; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693587
Filename
1693587
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