Hardware implementation of an optimized processor architecture for SOBEL image edge detection operator

This paper presents an implementation of a dedicated processor for image edge detection on field programmable gate arrays (FPGAs). The processor architecture is originally a Sobel based edge detection filter optimized to minimize memory utilization, redundant calculations and hence, overall logic resources used to implement the processor on FPGA. The optimization is achieved by exploiting the FPGAs´ high parallelism, flexibility and I/O bandwidth. Results show that our optimized processor architecture uses 22% less Adaptive Lookup Tables (ALUTs) 40% less dedicated logic registers and 10% overall logic resources utilization reduction over basic architecture in [1] when implemented on Stratix II EP2S60. The optimization makes the processor feasible to be used for applications like embedded video processing.