Title :
Dynamic flip-flop with improved power
Author :
Nedovic, Nikola ; Oklobdzija, Vojin G.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
Abstract :
An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. This is accomplished by equalizing the tpLH and tpHL of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase
Keywords :
flip-flops; logic design; dynamic flip-flop; keeper elements; logic embedding property; power-delay product; Clocks; Delay; Energy consumption; Flip-flops; Laboratories; Latches; Logic; MOSFETs; Power engineering computing; Topology;
Conference_Titel :
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-0801-4
DOI :
10.1109/ICCD.2000.878303
