Design of a reconfigurable FFT processor using Multi-objective Genetic Algorithm

Author

Hong, Pang Jia ; Sulaiman, Nasri

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. Putra Malaysia, Serdang, Malaysia

fYear

2010

fDate

15-17 June 2010

Firstpage

1

Lastpage

5

Abstract

This paper describes the implementation of Multi-objective Genetic Algorithm (MOGA) in a 16-point Radix-4 Single Path Delay Feedback (R4SDF) pipelined Fast Fourier Transform (FFT) processor in Verilog. The role of MOGA is to optimize the wordlength of the FFT coefficient and at the same time make sure the processor operates at acceptable Signal to Noise Ratio (SNR). Reducing the wordlength of FFT coefficient will contribute to lower Switching Activity (SA), thus lower power consumption is required for the operation of FFT processor.

Keywords

fast Fourier transforms; genetic algorithms; hardware description languages; FFT coefficient; Radix-4 single path delay feedback; Verilog; multiobjective genetic algorithm; pipelined fast Fourier transform processor; reconfigurable FFT processor; signal to noise ratio; switching activity; wordlength; Biological cells; Gallium; Hardware design languages; Optimization; Power demand; Signal to noise ratio; Switches; FFT processor; Signal to Noise Ratio; Switching Activity;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent and Advanced Systems (ICIAS), 2010 International Conference on

Conference_Location

Kuala Lumpur, Malaysia

Print_ISBN

978-1-4244-6623-8

Type

conf

DOI

10.1109/ICIAS.2010.5716157

Filename

5716157