DocumentCode
2550669
Title
Sensitivity levels of test patterns and their usefulness in simulation-based test generation
Author
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fYear
2000
fDate
2000
Firstpage
389
Lastpage
394
Abstract
Pattern sensitivity was proposed earlier as a property to guide simulation-based test generation for combinational or full-scan circuits. Sensitivity is a binary property, i.e., a pattern is either sensitive or not. In this work, we replace the binary sensitivity property by a property that assumes a range of values, called the level of sensitivity. We demonstrate that patterns with high levels of sensitivity tend to detect more faults than patterns with low levels of sensitivity, and therefore, it is important to consider the level of sensitivity of test patterns during test generation. We also describe a procedure for generating sensitive patterns with high levels of sensitivity
Keywords
logic CAD; logic testing; combinational circuits; full-scan circuits; pattern sensitivity; sensitivity levels; simulation-based test generation; test patterns; Circuit faults; Circuit simulation; Circuit testing; Cities and towns; Computational modeling; Computer simulation; Electrical fault detection; Fault detection; Genetics; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-7695-0801-4
Type
conf
DOI
10.1109/ICCD.2000.878313
Filename
878313
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