Title :
PEAS-III: an ASIP design environment
Author :
Itoh, Makiko ; Higaki, Shigeaki ; Sato, Jun ; Shiomi, Akichika ; Takeuchi, Yoshinori ; Tajima, Akira Ki ; Imai, Masaharu
Author_Institution :
Osaka Univ., Japan
Abstract :
In this paper, an architectural level processor design environment PEAS-III is proposed. Pipelined processors designed by this system can include multi-cycle operation, delayed branch and external interrupt. The data path and control logic of the processor are generated from the clock based micro-operation description of instructions. The ease of large design space exploration through experiments using several subsets of MIPS R3000 instruction set
Keywords :
application specific integrated circuits; instruction sets; parallel architectures; ASIP design environment; MIPS R3000 instruction set; PEAS-III; architectural level processor design environment; clock based micro-operation description; control logic; delayed branch; design space exploration; external interrupt; multi-cycle operation; pipelined processors; Application specific processors; Clocks; Educational institutions; Hardware; Logic; Pipelines; Process design; Registers; Specification languages; Timing;
Conference_Titel :
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-0801-4
DOI :
10.1109/ICCD.2000.878319
