Battle management onboard processing for SDI

The problem of the SDI (strategic defense initiative) onboard battle management processing is addressed. A brief overview of the general requirements for wartime space processing is presented, and the processing requirements which are specific to the battle management problem are discussed. Processor architecture and implementation using 05- mu m very high speed integrated circuit II (VHSIC II) superchip monolithic wafer-scale integration are considered. The sizing for both the VHSIC II and conventional LSI implementations is given. It is concluded that a spaceborne battle management processor capable of the throughput rate needed for the difficult SDI midcourse war scenario is feasible using advanced technology and an architecture tailored to the specifics of the problem. The critical effect of power consumption on spacecraft cost appears to militate against the use of conventional processor architectures and LSI implementation. Demanding specifications for survivability and reliability can be met by the use of a hierarchical fault-tolerant architecture based on the superchips. The battle management processor design, capable of over a billion operations per second, has a volume of 2.3 ft/sup 3/, a weight of 125 lb, and a power consumption of 1500 W. An LSI version with the same throughput would be significantly larger, heavier, and more power consumptive. The use of superchip or equivalent technology appears to be the key to achieving both the required high throughput and the 10-yr on-orbit lifetime.<>