Efficient logic optimization using regularity extraction

This paper presents a new method to extract functionally structures from logic netlists. It uses a fast regularity extraction algorithm based on structural equivalence. The goal of the proposed algorithm is the speedup of logic optimization of large circuits by reusing functionally equivalent structures of the design. It is particularly suited for circuits containing a large amount of datapaths. The regularity extraction algorithm uses an AND/XOR representation of the netlist to allow high correlation of functional and structural equivalence. It then extracts regular structures which can take any possible shape. The final optimization task is greatly reduced by optimizing only one copy of each regular structure while reusing the result for all other occurrences. In addition, structural regularity is widely preserved, resulting in higher packing density, shorter wiring length and improved delay during physical layout