A low-voltage CMOS LNA with multiple magnetic feedback for WLAN applications

Author

Vitzilaios, Georgios ; Papananos, Yannis ; Theodoratos, Gerasimos ; Vasilopoulos, Athanasios

Author_Institution

Microelectron. Circuit Design Group, Athens Nat. Tech. Univ.

fYear

2006

fDate

21-24 May 2006

Abstract

A CMOS low-noise-amplifier (LNA) topology that utilizes multiple monolithic transformer magnetic feedback is presented. The proposed topology permits negative and positive feedback to be applied constructively, in order to simultaneously neutralize the gate-drain overlap capacitance of the amplifying transistor and achieve high gain at high frequencies when driving an on-chip capacitance. It also allows for a stable design with adequate gain and large reverse isolation without noise figure (NF) degradation. Simulation results indicate voltage conversion gain of 17 dB, NF of 1.6 dB and third-order input intercept point (IIP3) of 13 dBm. The design is being implemented in a 0.13 mum CMOS technology

Keywords

CMOS analogue integrated circuits; circuit feedback; low noise amplifiers; low-power electronics; transformer magnetic circuits; wireless LAN; 0.13 micron; 1.6 dB; 17 dB; CMOS low-noise-amplifier topology; WLAN applications; amplifying transistor; gate-drain overlap capacitance; low-voltage CMOS LNA; multiple monolithic transformer magnetic feedback; on-chip capacitance; reverse isolation; CMOS technology; Capacitance; Degradation; Frequency; Negative feedback; Noise figure; Noise measurement; Topology; Voltage; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693630

Filename

1693630