DocumentCode :
2551509
Title :
Block interleaver design for high data rate wireless networks
Author :
Das, Barnali ; Sarma, Manash P. ; Sarma, Kandarpa K. ; Mastorakis, Nikos
Author_Institution :
Dept. of Electron. & Comm. Technol., Gauhati Univ., Guwahati, India
fYear :
2015
fDate :
19-20 Feb. 2015
Firstpage :
1000
Lastpage :
1005
Abstract :
With increasing data rates in wireless communication, quality of service (QoS) has become a major issue. This is more with fading channels transmitting huge volumes of data. QoS is degraded by intersymbol interference (ISI) and related errors. One of the simplest and convenient techniques to overcome such errors is interleaving, which is used efficiently in wireless applications. It has found applications for combating burst errors that creeps up in the channel during transmission. In this paper, an efficient model of a block interleaver using a hardware description language (Verilog) is proposed. The proposed technique reduces consumption of FPGA resources to a large extent, which implies low power consumption.
Keywords :
fading channels; hardware description languages; intersymbol interference; quality of service; radiocommunication; FPGA; ISI; QoS; Verilog; block interleaver design; burst errors; fading channels; hardware description language; high data rate wireless networks; intersymbol interference; quality of service; wireless communication; Binary phase shift keying; Field programmable gate arrays; Mathematical model; Power demand; Receivers; Transmitters; Wireless communication; Block Interleaver; Device utilization; FPGA; Power consumption; Verilog;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing and Integrated Networks (SPIN), 2015 2nd International Conference on
Conference_Location :
Noida
Print_ISBN :
978-1-4799-5990-7
Type :
conf
DOI :
10.1109/SPIN.2015.7095305
Filename :
7095305
Link To Document :
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