Title :
A low power 256 KB SRAM design
Author :
Bhaumik, Basabi ; Pradhan, Pravas ; Visweswaran, G.S. ; Varambally, R. ; Hardi, A.
Author_Institution :
Dept. of Electr. Eng., IIT, New Delhi, India
Abstract :
In this paper a low power SRAM design is presented. Existing SRAM architectures used in SGS Thomson were studied to explore the possibilities in bringing down power dissipation in various blocks. A Divided word line (DWL) scheme was implemented. Particular emphasis was put to reduce power consumption in decoders. A new critical path model was introduced for schematic simulation. This lowered the simulation time considerably. Simulation results confirmed the effectiveness of our approach
Keywords :
SRAM chips; integrated circuit design; low-power electronics; 25 KB; computer simulation; critical path model; decoder; divided word line; low power SRAM design; Cache memory; Circuits; Energy consumption; Microelectronics; Microprocessors; Random access memory; Reactive power; Read-write memory; Research and development; Working environment noise;
Conference_Titel :
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location :
Goa
Print_ISBN :
0-7695-0013-7
DOI :
10.1109/ICVD.1999.745126
