DocumentCode
2551795
Title
IDDQ-testability of tree circuits
Author
Blanton, R.D.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1999
fDate
7-10 Jan 1999
Firstpage
78
Lastpage
86
Abstract
The quality of CMOS circuits can be increased by performing IDDQ testing. For regular circuits constructed from identical modules, defects localized to a single module detectable by current testing can be sensitized by exhaustively applying all input patterns to each circuit module. Regular circuits for which every module in arbitrarily large circuit can have all input patterns applied are defined to be IDDQ-testable. The IDDQ-testing properties of a class of regular circuits called tress are investigated. We present the conditions for one-dimensional and tree array circuits to be IDDQ-testable. We also present conditions for these circuits to be CIDDQ-testable, that is, IDDQ-testable with a constant number of tests independent of the circuit´s size. Practical circuits such as comparators and carry-lookahead adders are used to illustrate the derived conditions
Keywords
CMOS integrated circuits; adders; comparators (circuits); integrated circuit testing; CMOS tree circuit; IDDQ testing; carry lookahead adder; comparator; one-dimensional array; Adders; CMOS logic circuits; Circuit faults; Circuit testing; Current measurement; Integrated circuit interconnections; Performance evaluation; Power supplies; Semiconductor device modeling; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location
Goa
ISSN
1063-9667
Print_ISBN
0-7695-0013-7
Type
conf
DOI
10.1109/ICVD.1999.745128
Filename
745128
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