Design exploration with an application-specific instruction-set processor for ELA deinterlacing

Achievable performance gains, when accelerating applications using ASIPs, with a good sequence of specialized instructions, depends on the applications´ available parallelism, and possibilities for optimizations and transformations. The type and number of operations, and the number of data transfers of the application are also critical factors. Much progress has been done on ASIP customized instruction-identification and selection research; they are usually based on operation clustering. In this paper, we propose to minimize the number of data transfers during execution of specialized instructions sequence by storing temporary values in user-defined registers. The method avoids costly data transfers and allows parallel processing of demanding computations. This method is applied to the design of an ASIP dedicated to edge line average deinterlacing, an algorithm used in HDTV. Experimental results show that our design method applied to this application, yields a speedup factor larger than 18