A 33-dBm 1.9-GHz silicon-on-insulator CMOS stacked-FET power amplifier

A single-stage stacked-FET power amplifier (PA) is demonstrated using a 0.28-mum silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. The stacked-FET PA has been designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. The measurement results show that, with a 6.5-V supply, the PA achieves a small-signal gain of 13.2 dB, a saturated output power of 33 dBm, and a maximum power-added-efficiency (PAE) of 47% at 1.9 GHz. This is the first reported stacked-FET PA in submicron SOI CMOS technology that delivers multi-Watt output power in the GHz range. It also maintains high power efficiency over a wide range of supply voltages.