FPGA implementation of a new family of stack filters

Several field programmable gate array (FPGA) implementations of stack filters, a relatively new class of nonlinear filters, are described. These filters are a generalization of the well-known stack smoothers that overcomes the last one´s limitations on frequency response. The design used joins a modified version of the bit-serial method, already used with stack smoothers, with an implementation of these filters´ new features. The parallelism contained into the algorithms involved makes the FPGA, with its remarkable ability to implement complex digital systems, to be especially appropriate for this application. It was found that the properties of one of the mathematical structures involved in the stack filter theory could help to improve significantly the filter´s performance and to optimize its use of hardware resources. The realizations designed include both parallel and nonparallel versions of stack filters and the WOS (weighted order statistic) subset of them. The experimental results obtained illustrate the speed-complexity-performance trade-off of these implementations and show that it´s possible to apply these filters in real-time hardware processing of signals or images.