Multi-valued logic synthesis

Author

Brayton, Robert K. ; Khatri, Sunil P.

Author_Institution

California Univ., Berkeley, CA, USA

fYear

1999

fDate

7-10 Jan 1999

Firstpage

196

Lastpage

205

Abstract

We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package

Keywords

Boolean functions; circuit optimisation; logic CAD; multivalued logic circuits; logic manipulation; logic optimization; logic representation; multi-level optimization package; multi-valued logic synthesis; Buildings; Circuit synthesis; Encoding; Logic circuits; Logic design; Multivalued logic; Network synthesis; Optimization methods; Packaging; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Conference_Location

Goa

ISSN

1063-9667

Print_ISBN

0-7695-0013-7

Type

conf

DOI

10.1109/ICVD.1999.745148

Filename

745148

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2552254