Efficient simulation for hierarchical and partitioned circuits

This paper presents new, highly-efficient techniques for simulating extremely large circuits, assuming that hierarchical design techniques have been used. Both hierarchical and partitioned circuits consist of a master circuit and several sub-circuits. Hierarchical circuits permit sub-circuits to be reused, while partitioned circuits permit only a single use of each sub-circuit. Both types of circuits permit multiple levels of hierarchy. In partitioned circuits, triggering is used to perform simulations that are several times faster than Levelized Compiled Code (LCC) simulation. For hierarchical simulation, the concept of boundary activity is introduced. Optimization with respect to boundary activity can produce simulations that are much faster than ordinary flat simulations. It is further shown that hierarchical design can permit the efficient simulation of circuits that cannot be simulated on a single workstation using ordinary flat simulation. Aggressive use of hierarchy is used to demonstrate the simulation of circuits containing as many as four billion (4,000,000,000) gates