Efficient path metric access for reducing interconnect overhead in Viterbi decoders

Efficient management of the path metric memory and minimization of interconnection networks between the memory and addcompareselect unit (ACSU) are always the key concerns on the design and implementation of Viterbi decoders. In this paper, we derive a set of simple equations to partition the memory into P banks such that the equivalent memory bandwidth can be increased with very simple interconnection networks. Compared with the previous work, our proposed approach reveals the following superiority: (1) Each memory bank can be treated as a local memory of a specific ACS; thus, the interconnection network is simplified. (2) The P memory banks can be merged into only two pseudo-banks regardless of the number of ACS operations. This not only further reduces the hardware requirements of address generation, but also makes smaller the required memory space