Analytical expressions for power dissipation of macro-blocks in DSP architectures

Power minimization is an important objective in present day VLSI design. Macromodels for power dissipation can be used to estimate power at a high-level of abstraction. High-level power estimation methods provide the designer with more flexibility to explore design trade-offs early in the design cycle. In this paper, we present closed-form analytical expressions for power consumption of macro-blocks in terms of the word-statistics. We present an analytical expression for total bit transition activity of a signal line in terms of the word-statistics. We also present analytical power models for macro-blocks in DSP architectures in terms of total bit transition activity and other parameters. Experimental results validating the analytical expressions are also included in this paper