Hardware architecture and trade-offs for generic inversion of one-way functions

Time-memory trade-off (TMTO) is a twenty five years old technique for inverting one-way functions. The most feasible implementation of TMTO is in special purpose hardware. Till date the work on hardware architecture for TMTO has been somewhat sketchy. In this paper, we describe a systematic architecture for implementing TMTO. We break down the offline and online phases into simpler tasks and identify opportunities for pipelining and parallelism. This results in a sufficiently detailed top-level architecture. To the best of our knowledge, such architecture does not appear in the literature