Title :
Performance driven synthesis for pass-transistor logic
Author :
Liu, Tai-Hung ; Ganai, Malay K. ; Aziz, Adnan ; Burns, Jeffrey L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
For many digital designs, implementation in pass-transistor logic (PTL) has been shown to be superior in terms of area, timing, and power characteristics to static CMOS. Binary Decision Diagrams (BDDs) have been used for PTL synthesis because of the close relationship between BDDs and PTL. Thus far BDD optimization for PTL synthesis has targeted minimizing the number of BDD nodes. This strategy leads to smaller PTL implementations, but it can result in circuits of poor performance. In this paper we model the delay of PTL circuits derived from BDDs, and propose procedures to reduce the worst-case delay or the area-delay product of such circuits. The experimental results show a significant improvement in the delay (30%) or area-delay product (24%) for the ISCAS benchmark circuits
Keywords :
Boolean functions; binary decision diagrams; circuit optimisation; delays; integrated logic circuits; logic CAD; multivalued logic circuits; timing; BDD optimization; Boolean functions; ISCAS benchmark circuits; MUX structure; area-delay product; delay model; multi-level logic; pass-transistor logic; performance driven synthesis; worst-case delay; Binary decision diagrams; Boolean functions; CMOS logic circuits; CMOS technology; Circuit synthesis; Data structures; Logic circuits; Logic functions; Optimization methods; Timing;
Conference_Titel :
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location :
Goa
Print_ISBN :
0-7695-0013-7
DOI :
10.1109/ICVD.1999.745184