Title :
Heuristic technology mapper for LUT based FPGAs
Author :
Bhat, Chitrasena ; Chiplunkar, Niranjan N.
Author_Institution :
Dept. of Comput. Sci. & Eng., S.J. Coll. of Eng., Mysore, India
Abstract :
One of the main objective in the process of mapping a circuit onto a look-Up Table (LUT) based FPGA is to minimize the number of LUTs required to implement the circuit. A new top-down technology mapper algorithm is discussed in this paper which aims at minimizing number of LUTs needed for mapping the digital circuit. The algorithm makes use of combination of node selection and covering heuristics using which maximum number of DAG nodes are covered by a selected LUT. The results obtained are better than Chortle, Level-map and Flow-map-r technology mapper algorithms
Keywords :
directed graphs; field programmable gate arrays; logic design; table lookup; FPGA; LUT; digital circuit design; directed acyclic graph; field programmable gate array; heuristic top-down algorithm; logic synthesis; look-up table; technology mapper; Circuit synthesis; Combinational circuits; Costs; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic gates; Network synthesis; Production; Table lookup;
Conference_Titel :
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location :
Goa
Print_ISBN :
0-7695-0013-7
DOI :
10.1109/ICVD.1999.745187
