Title :
A 1.7mW all digital phase-locked loop with new gain generator and low power DCO
Author :
Chao, Tzu-Chiang ; Hwang, Wei
Author_Institution :
Dept. of Electron. Eng., National Chiao-Tung Univ., HsinChu
Abstract :
In this paper, a new architecture and algorithm for all digital phase-locked loop (ADPLL) is proposed. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator (DCO) structure for low power, small area is presented and its frequency range is from 200 MHz to 750 MHz with a supply voltage 1.2v. The total power consumption of ADPLL is 1.7mW. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption. This ADPLL is designed and implemented by TSMC´s 0.13mum CMOS technology
Keywords :
CMOS integrated circuits; UHF detectors; UHF oscillators; digital phase locked loops; low-power electronics; phase detectors; 0.13 micron; 1.2 V; 1.7 mW; 200 to 750 MHz; CMOS technology; all digital phase-locked loop; digitally controlled oscillator; frequency comparator; gain generator; phase detector; CMOS technology; Clocks; Digital control; Energy consumption; Oscillators; Phase detection; Phase frequency detector; Phase locked loops; Power generation; Voltage control;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693721
