Title :
An illustration of 90nm CMOS layout on PC
Author :
Sicard, Etienne ; Dhia, Sonia Ben
Author_Institution :
INSA, DGEI, Toulouse, France
Abstract :
The 90nm CMOS process technology, in commercial production in 2004, includes copper interconnects, 6 to 12 metal layers and 5-10 types of MOS devices. In co-operation with ST-microelectronics, the layout editor/simulator Microwind has been configured to support this state-of-the art CMOS process for research and training purpose. This paper describes the recent developments and their application to microelectronics training.
Keywords :
CMOS integrated circuits; MIS devices; integrated circuit interconnections; integrated circuit layout; 90 nm; CMOS process technology; Cu; MOS device; ST-microelectronics; copper interconnects; layout editor/simulator Microwind; metal layers; microelectronics training; Art; CMOS logic circuits; CMOS process; CMOS technology; Central Processing Unit; Circuit simulation; Computational modeling; Copper; Integrated circuit interconnections; MOS devices;
Conference_Titel :
Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on
Print_ISBN :
0-7803-8777-5
DOI :
10.1109/ICCDCS.2004.1393404
