Design considerations of Sub-100nm Dual Material Gate Fully Depleted Silicon On Insulator (DMG-FD-SOI)

This paper presents the results of extensive simulations on the characterization of asymmetrical channel device, namely Dual material Gate Fully Depleted Silicon On Insulator (DMG-FD-SOI) in the sub-100nm dimensions with emphasis on the analog, radio frequency (RF) performances and short channel effects (SCEs). The obtained results may serve as useful guidelines to get a basis overview of this gate-material engineered architecture. Improvement on cut-off, int _T and maximum oscillation frequency, int _max are observed with the applied DMG design. Better SCEs and analog performances which are open loop gain (g_m/g_d) and I_ON/I_OFF ratio can be achieved with reduced silicon thickness, T_si but with drawback on degraded int _T and int _max. For shorter gate length design of DMG in sub-100 nm dimension, higher threshold voltage, V_TH can be applied for SCEs suppression with insignificant degradation on the analog and RF point of views.