Title :
A new structure for capacitor-mismatch-insensitive multiply-by-two amplification
Author :
Zare-Hoseini, Hashem ; Shoaei, Omid ; Kale, Izzet
Author_Institution :
Dept. of Electron. Syst., Westminster Univ., London
Abstract :
A new approach to achieve a switched-capacitor multiply-by-two gain-stage with reduced sensitivity to capacitors´ mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (times2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a much smaller influence on the accuracy of the gain of two (times2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35mum CMOS technology
Keywords :
CMOS integrated circuits; analogue-digital conversion; network analysis; operational amplifiers; switched capacitor networks; 0.35 micron; CMOS technology; analog-to-digital converters; capacitor mismatch; circuit level analysis; input capacitors; multiply-by-two amplification; operational amplifier; switched capacitor; Capacitors; Circuit analysis; Digital signal processing; Energy consumption; Feedback; Operational amplifiers; Sampling methods; Transfer functions; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693724
