Faster delay modeling and power optimization for on-chip global interconnects

The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient delay modeling of interconnection is needed for high speed ICpsilas. This paper presents a closed-form expressions for RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation of delay after the design clock tree has been laid out and the design is fully routed. Evaluation of this analytical model is several orders of magnitude faster than simulation using SPICE. The power consumption of interconnects has become an important issue as technology scales down. For voltage mode signaling optimum line width that minimizes the total transient power dissipation is discussed in this paper. Closed form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. Considering inductance in repeater insertion significantly saves the repeater area and power consumption.