GeneSys: a leaf-cell layout synthesis system for GHz VLSI designs

Author

Basaran, Bulent ; Ganesh, Kiran ; Lau, Raymond ; Levin, Artour ; McCoo, Miles ; Rangarajan, Srinivasan ; Sehgal, Naresh

Author_Institution

Design Technol., Intel Corp., Santa Clara, CA, USA

fYear

1999

fDate

7-10 Jan 1999

Firstpage

448

Lastpage

452

Abstract

We present a new VLSI layout tool that synthesizes leaf-cell layouts for custom designs as well as standard cell and datapath libraries. GeneSys takes a leaf-cell schematic and a variety of top-down constraints to produce a layout for the circuit. The tool consists of five main components: placer, router, compactor, reliability analyzer and family generator. The system features new 2-D device placement and routing algorithms driven by reliability constraints. A Cell Architecture Rules feature allows customization of the tool to various layout styles. The family generation feature allows rapid synthesis of layout families from template cells. Initial usage statistics show a 2-4X mask designer productivity improvement for a variety of cells

Keywords

VLSI; application specific integrated circuits; circuit layout CAD; digital integrated circuits; high-speed integrated circuits; integrated circuit layout; network routing; 2D device placement algorithm; 2D routing algorithm; GHz VLSI designs; GeneSys; VLSI layout tool; cell architecture rules feature; compactor; custom designs; datapath libraries; family generator; leaf-cell layout synthesis system; placer; reliability analyzer; reliability constraints; router; standard cell libraries; top-down constraints; Educational institutions; Frequency; Libraries; Logic design; Microprocessors; Optimization methods; Productivity; Routing; Statistics; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, 1999. Proceedings. Twelfth International Conference On

Conference_Location

Goa

ISSN

1063-9667

Print_ISBN

0-7695-0013-7

Type

conf

DOI

10.1109/ICVD.1999.745196

Filename

745196